Memory Bus Widths

Right. Where to start??

Came off the A+ course, and now I want to claify this, but I know that even beofre I post this, it isnt going to make sense.

Ok.

Was informed that basically, if you had a 64 bit bus width (as on Pentiums?) you needed to put 64 bit's worth of memory in the banks, otherwise it would not work.

I.E 64bit bus would need 2 x 72 pin SIMMS (apparently 32bit each?) otherwise it wouldnt work...

IS that right??

If so, then what happens if you added 4 SIMMS, 72pin each? that would total 128 bits. Apparently this extra would be ignored, but does that not mean that the RAM on the sticks would also be ignored??

The tutor said we may of been getting confused with memory address and something else, alas she never bothered to explain it.

Someone I spoke to came up with a theory, that RAM operates on a stack system basis. So if we use the above example, the system would use the amount of RAM that the system recognised in the range of bits is needed (in this case the first 2 SIMMS) and then use the other 2 as 'storage', simply passing up the data into the first 2 sticks as the space on them free up...

True/False?

And here's the other bit. If Pentiums already run at 64 bit bus width, what is so special about these new AMD64's?

Also, how are the amount of pins relational to how many bits a SIMM or DIMM is?

Thanks to those who read this, if it dont make sense please let me know!!

Now my head is going to explode.

Hong

Ok. First, shoot your tutor. Second, shoot that "someone". Third, quit this course. WOW! Just kidding!;) :D

It's way too early and I've had way too little coffee to even know where to begin reponding on this one Hong. My brain just ain't up to it yet. ;):D Definately should (hopefully) provoke some good dicussion here though. I understand what you're after, though there is some confusing and mixing of of things here for sure.

PS. And just think, you're paying to get these cronic headaches. Come to think of it, I guess so are we.:rolleyes: Just kidding!

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Ok. First, shoot your tutor.Third, quit this course.

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If only you knew how many times I thought about doing this...

Right, SOMEBODY GET SOME COFFEE FOR THE DOC!! :D:D

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Definately should (hopefully) provoke some good dicussion here though.

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Me too

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I understand what you're after,

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I'm glad someone does :rolleyes:

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And just think, you're paying to get these cronic headaches.

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Well the course is free for me, I just feel sorry for the PAYING clients...:mad:

http://home.ripway.com/2004-10/183923/cofeemaker.jpg

Here doc (and any others)...help yourself to a virtual coffee, on me :D:D

On onto the serious stuff... :p

LOL. Thanks, but with some of the questions you ask lately Hong "virtual" just won't cut it. In fact, something even stronger may be in order.:p

Hey ya all

As soon as anyone is brave enough to try and answer this one, go right ahead.

Not pushing or anything, just dont want this thread to go dead ;)

So Is noone brave enough to break this to me gently? :)

It is ambush time!

Now nail that instructor's feet to the floor and get a answer!
Have IT,[can not be human] correct what they did not explain.

I taught industrial hydraulics at the college level and boy, do I wish I was a fellow student. :D
So take your question and cram it down their throat again and agaain until they do. Then please post what they finally give you.


:D
Have fun!
I be waiting.

Do you have a copy of Upgrading and Repairing PC's, Hong? Because there is an excellent section on memory there, that would probably explain a lot of this more easily than any of us can here.

As far as the difference between the P4 and AMD64, the limiting factor isn't anything to do with bus width, but rather with the internal registers.

The P4, and 32-bit CPUs in general can address 2 ^ 32 bits which equals 4294967296 bits or 4Gb.

The AMD64 can address 2 ^ 64 bits = 18446744073709551616 bits or 17 billion GB!

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Originally posted by DrMDJ
with some of the questions you ask lately Hong "virtual" just won't cut it. In fact, something even stronger may be in order.:p

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I have been wanting to say this for months. :D

And if any of you need your coffee fix without moving from the 'puter, then this is what you need :D

http://articles.pimprig.com/featured...ne_machine.php

Thanks all.

Sparks: No, I dont have a copy of Upgrading and Repairing PC's, who is the author? I want to make sure I get the right copy. Thinking about it, I think I may have heard of thise book before.

Kazz: Have I been that bad? :( :o

Train: I will re-ask again tomorrow. Lord be with me, I shall post back if I dont get arrested!!

Thanks again.

Hong

Scott Mueller and this is a Amazon.com link.

Snd here is the latest version of the book. Pricey, but he does a darn good job. My copy is way older version wise.

Thanks Train ;)

Yep, if you are doing A+, or just need to know about computer hardware, that book is a must have. It is a true goldmine of information.

You can get the 16th (latest) edition for around £30 from:

http://www.amazon.co.uk/exec/obidos/...604412-4086812

or:

http://www.compman.co.uk/scripts/browse.asp?ref=687758

Its in my xmas list :)

Or unless anyone wants to donate £30 to the 'Hong A+ Charity' :D:D:D

Well I've been out of pocket for a couple days and expected to come back and find this thread pages long. I see you've gotten some input here Hong, now I'll throw in my 2 cents.

First, on the issue of what distiguishes a 32-bit from a 64-bit processor... Spark's mentioned it was based on the internal registers of the processor. That's true. But it is specifically this size in relation to the integer registers that are the key. Other registers (eg. floating point, MMX, SSE, etc) can and are much larger than 32 bits even in processors categorized as 32-bit.

Now, memory access and addressing... Data/instructions flow between memory (or the memory controllers) and the processor over a bus (a series of electrical connections), specifically the memory bus. With the 32-bit processors this memory bus is external to the processor itself (that changes with something like the AMD 64, but we won't go in to that cause it's not relevant here). What constitutes the memory bus is divided in to three buses (sets of lines) really: the data bus, the address bus and the control bus. We'll ignore the control bus here since it doesn't really tie in to any of your questions. It is over the data bus that the actual bits of data (data meaning data or instructions) flow. And it is over the address bus that the addresses of the memory that are to be read or written (via the data bus) are communicated between the cpu and memory controller(s). Now how many bits (the size) of these buses is tied to the processor (processor type/family) that the motherboard/chipset is designed for. But, the size of the indiviual buses (data, address, control) need not and aren't the same size (handle the same number of bits). Why? A number of reasons, more than are really necesary to go in to here I think. But in large part because if you think back to the fact that a bus is a series of physical electrical connections then you can see why it would be beneficial from certain standpoints to minimize the number of connections whereever possible (both in terms of pins on a processor and traces on a motherboard). Anyway...

OK... Now since the Pentium and on up through today 32-bit processors have had data buses that are 64 bits wide (ie. data is transferred in 64 bit size chunks). Why? Well that gets in to some aspects of procesor architecture and efficiency and are really beyond this thread (and beyond what my head can handle right now), but if someone else wants to take up that, then.... For now I just say accept this as part of the design of 32-bit processors. It's (and as Sparks mentioned) this 64 bit data bus width/size that often confuses people (including you) when it comes to a processor being a 32-bit processor. The fact that memory data bus transfers in 64-bit chunks has nothing to do with the/a processor being called (being) a 32-bit processor.

When you have a 64-bit data bus size it means that any transfers between memory (memory controllers) and the cpu must be exactly 64 bits. No more, no less. You might hear the term that a full "bank" must be transferred at a time, but the term "bank" is a bit nebulous and has different meaning in different situations when it comes to memory. Anyway... While the data bus may have a width of 64 bits (64 data lines) that doesn't mean a ram stick has to or does have 64 data lines (can transfer 64 bits of data in one shot). And with 72 pin simms this is the case. These simms have 32 data lines and, therefore, can only transfer 32-bits of data at a time. So, in order to fullfill the requirement of transferring 64 bits at a time data must be read/written from/to 2 of these simms at one time (again, not to get in to "banks" but that's why you here that 2 72-pin simms equal a bank, and why these simms must be replaced/added in (matched) pairs, with processors relying on a 64 bit data bus). Now with dimms (168 or 184 pin) there are 64 data lines (meaning 64 bits at a time can be transferred from a given dimm module/stick). As a result, a single dimm can fullfill any transfer requirements of a 64 bit data bus (and is why dimms can be added/replaced individually).

So to summarize on your question about filling banks with 64 bit buses... The 64 bit bus referred to is the memory "data bus". Transactions (the amount of data moved) over this bus must equal its size (64 bits), and this number of bits (at least in one sense) is considered to consitute a bank of memory. So, to meet this requirement requires that one memory bank be accessible and moveable at a time. Anything less won't work (to use your words) With 72-pin simms this means 2 sticks, which represent a bank of data lines. With a dimms this means 1 stick, which represents a bank of data lines).

In regard to you asking about 2 vs 4 simms... Again, it's about the "banks" The 4 (72 pin) simms represent 2 banks. They won't be ignored, just addressable as a different bank (again that nebulous term). As such they just represent a different addressable range of memory.

Ok, so much for the data bus and such, now for the address bus... The number of (lines) bits comprising an address bus, its width, dictates how much memory can be used/addressed. For a 32 bit wide address bus it means that up to 2^32 memory addresses can be accessed. Typically with what we know as 32-bit processors the address bus just happens to be 32 bits wide, meaning that 2^32, or 4gb, of memory can be addressed. Now there are a couple exceptions to this in the "32 bit family". Processors like the Pentium Pro and Pentium II actually provide for a 36 bit memory address bus, meaning they "could" address up to 64gb of memory. But for practical purposes (and simplicity) the address bus of 32 bit processors can basically be thought of as 32 bit and capable of addressing 4gb of main memory.

Now a note here (and it relates to theoretical vs implemented aspects of things)... Sparks said that the current line of 64 bit processors can address up to 2^64 bits (addresses) of memory. Thats actually not true. The current line of AMD and Intel 64 bit processors do not have a full 64 bit implemented address bus. With the AMDs (AMD 64) the address bus is actuall 40 bits, and with the Intels (Itanium) its 44 bits. Not that this is a big deal because few situations are going to call for needing to access more memory than even the current 32 bit procesor memory buses can. But maybe it highlights/emphasizes a semi-important (and related to this thread) point. Namely that whether a processor is 32 or 64 bit really has little (practically) to do with how much memory it or motherboard chipsets that support it can address.

On the issue of pins on a simm/dimm (stick) and the amount of memory on a stick... Do the number of pins relate absoultely to the amount of memory on the stick? Obviousl not, since you have the same number of pins on a given simm or dimm yet simms/dimms come in different memory capacities. Do the number of pins on a simm/dimm dictate how much addressable memory could be on a stick? Ultimately, yes. The reasons is that while there are "X" (30, 72, 168, 184, whatever) pins that connect to a memory slot, not all these are used to carry the bits that comprise the address of the memory cell that is to be addressed (read/written). Pins must be devoted to other purposes: carrying the data and control. Truth is that on any given (memory) module (be it a simm or a dimm) there are relatively few address pins (lines). In fact a fewer number of pins are devoted to carrying a memory address are used than actually would be (are) needed to address the amount of memory on the stick. Because simms/dimms need to have a defined number of pins (corresponding to the pins in their slots, corresponding to the traces between a slot and the memory controller, ...) "pin real estate" is at a premium. That's why when it comes to address pins (lines) simms/dimms are designed to address memory on a stick (the cells) in terms of rows and colums (and even "bank", again that nebulous term that here means something different than what it meant before) . And instead of the actual (full) address of a memory cell being dealt with, addresses are dealt with in terms of a row and a colum address (and perhaps bank). And these row/column addresses are selected (transmitted to pins on the memory module) in two steps: row first, then column (generically the process is called address multiplexing, and is handled by the memory controller). Anyway... By being able to split addressing in to rows and colums (of cells) allows the number of pins used/needed to be reduced. Now back to the point (there was one wasn't there?)... Given the fact that there are a predefined number of pins on a simm/dimm, coupled with with specific needs for other functions that pins must be devoted to, means there are a limited number of pins available for addressing (even by row, column, bank means).

So as a result (and without getting specific in terms of the amount), yes, there is a relationship (limit) in terms of the amount of memory there can be on a memory module and the number of pins it has.

Well as usual, once I get started.... I hope I addressed your questions Hong. And I apologise if I jumped around and hope I didn't confuse things even more. Then again, if I did then turn about is fair play. You had my head spinning when I first read your post, it's only fair if I made yours spin in answering.

PS. I still say shoot the teacher.

aha........!!!!

Well there you have it, another masterful explanation from the Doc :)

I should have explained myself better when referring to the AMD64, that 2^64 bits is what it could theoretically address, rather than what it actually does at the moment - I guess it'll be some time before we start moaning about the 1024GB limit imposed by 2^40 addresses, let alone the 17,179,869,184 GB limit :D

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I guess it'll be some time before we start moaning about the 1024GB limit imposed by 2^40 addresses, let alone the 17,179,869,184 GB limit

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LOL. I think even the gamers will have a hard time taxing that limit Sparks. And quite frankly, if they did then they deserve to run out of memory. Heck, at 4gb.:D

Bloody hell Dr!!

That was an excellent explanation, my god. It is clearer in my head now, and I thank you for that!!

I wont lie and say its all crystal clear...I need more in-depth knowledge on these regions of a PC to fully comprehend it all I think, but you did a damn site better job then any teacher I've known!

My head spinning? Yes, to say the least. :D

So, since the current address bus width @ 40/44 bits is huge in comparision to what we would ever need, would this be developed further? Or do you think it will just be left st that, even with Processor technological advances?

So, to summarise, there are 3 buses to consider:

1) The data bus, which carries the info
2) the address bus, which carries the info needed to know which address range is being read/written to
3) the controller bus which I presume is used for 'controlling' the flow of data

The data bus on current mobo's (with 32bit cpu) is 64 bit, which means it transmits data in 64bit chunks. It has to transmit at that amount, no less. So the RAM Banks on a mobo has to fulfill this, primarily by using 2 x 32bit modules or 1 x 64bit module (at least).

Any more modules (excess bits of you like) are then seen as a seperate address range which the CPU can read/write to.

Am I right? Have I grasped it??

Thanks

Hong...phew

LOL. You actually made sense of what I said? WOW, you're better than me Hong.:D Hopefully it did make some sense. If you think your head's swimming, well then join the club. This isn't the kind of stuff one deals or thinks about every day (no sane person would:eek:).

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So, since the current address bus width @ 40/44 bits is huge in comparision to what we would ever need, would this be developed further? Or do you think it will just be left st that, even with Processor technological advances?

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Who's to say. But remember, it wasn't all that long ago people were saying "why would we ever need" things like 32-bit or 64-bit processors, hard drives that required more than 28-bits to address them, etc, etc.

And for your summary on the bus functions... You've essentially got it with the exception of perhaps a couple points.

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So the RAM Banks on a mobo has to fulfill this, primarily by using 2 x 32bit modules or 1 x 64bit module (at least).

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Not exactly. Obviously, memory modules (chips, sticks, what ever you want to look at) are much bigger than 64 bits in size. It's not really the number of bits/bytes on a chip, the stick/module, even in the whole bank of memory you want to focus on. What's important is the number of data lines a given stick of memory (be it a simm, dimm, etc) has, and therefore the number of bits that can be transferred to/from that stick (to the memory controller and then on) at one time (not the number of bits on it in total). Now our rules/conventions state that, in the context of our data bus width being 64 bits, that we must be able to transfer 64 bits at a time. This requires 64 data lines. Where the "banks" come in here (in this context) is that from the standpoint of the motherboard chipset, or more specifically the memory controller(s), these banks are a logical/physical grouping/organization of the memory sticks in such a way that can provide (sets of) 64 data lines (so that the required 64 bits of data is capable of being transmitted in one shot). The number of sticks it takes to comprise a bank depends on the number of data lines provided on an individual memory module (relative to the size (in bits) of the data bus). With 72-pin simms this means 2 sticks are required to form a bank, with dimms only one stick is needed. The stick/sticks grouped in to a bank may (and certainly will) have much more than 64 bits of memory cells on it/them (megabytes, gigabytes). That's irrelevant. What is relevant is the fact that no matter what memory address range of cells that might exist on the stick/sticks, and no matter which of these addresses needs to be accessed, the access can take place in a 64-bit chunk. Now, you have to have at least one back of memory in a system (obviously, to provide the needed data lines to fill the data bus). But you can have more than one bank (and often do). This isn't "excess", just part of the overall memory address space (range of addresses). The memory just happens to be spread over different banks, and addressable by the controller(s) as such. By the way... This "bank" stuff (as well as the row/column addressing I mentioned earlier) is only relevant to the motherboard chipset and memory controllers. The processor doesn't see memory, deal with in it, in these terms. To the processor there is simply a linear range of addresses (8 bits each) going from 0 to "what ever" address.
Make sense? Any clearer? Worse than before?

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Make sense? Any clearer? Worse than before?

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Erm, hmm...well... not worse at all, but not any clearer (YET!)

I need to read this over a few more times after lunch...

Thanks Doc

BTW, something I do understand is that the amount of Memory in a module is not relevant to its capacity to transfer in bits...

Hmm..Actually, it makes sense now. Just read it over again and indeed it makes sense.

Oh my!! :eek:

The one thing I learnt here is that the CPU doesnt deal with the memory directly, it deals with the memory controller yes? Coz in class, the tutor is always banging on about how the CPU talks with the Memory, which isnt true at all.

My shotgun is in the mail, with a full supply of ammo. :D

Hong

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The one thing I learnt here is that the CPU doesnt deal with the memory directly, it deals with the memory controller yes? Coz in class, the tutor is always banging on about how the CPU talks with the Memory, which isnt true at all.

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Well as we have said before, if the teacher says the "blah, blah, blah", then that's the way it is.;)

But yes, you are right. The cpu does not deal directly with the memory. It does so via the motherboard's core logic chipset (ooow, one of those fancy computer terms:D), and in turn the chipset talks through the memory controllers to the ram sticks.

Sorry for confusing things. Of course all of this is just the "broad strokes" of things. As I (think I) said before, a lot of details, nuances, etc are omitted. Hmmm. Maybe when it's all said in done your teacher actually had it right. Maybe it is just best to say "Here's the way it works, end of story. Just accept it.":D

Thanks to everyone that participated, its been a steep learning curve but we got there in the end.

Hong

:D:D:D

Till the next time...

Not wishing to try and muddy the waters any further, but it might be worth mentioning that the AMD64 does deal directly with memory, as they have moved the memory controller circuits onto the CPU die itself. Whether this will be the way of the future, and all processors will follow suit, remains to be seen.

http://www.amd.com/us-en/Processors/...5E9495,00.html

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Not wishing to try and muddy the waters any further, but it might be worth mentioning that the AMD64 does deal directly with memory, as they have moved the memory controller circuits onto the CPU die itself. Whether this will be the way of the future, and all processors will follow suit, remains to be seen.

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Not too confusing Sparks, managed to get that one ;)

Muddying even further....

Yes, I touched on the change in the AMD 64 in my first post and said I'd let it lie at that time.

Yes, the memory controller(s) have been moved "on-die" with the 64's, but there's a couple things this does and doesn't mean. First, having the controllers (and the paths to them) on-die does not actual mean these things are part of the actual "processor", simply that they are part of the "processor package" (which includes the cpu and...). Second, whether on-die or off, the memory controller(s) are still in the path, electrically and logistically speaking, between the actual cpu and memory. So the cpu still does not truely communicate directly with memory.

...and when I see the word memory, Northbridge comes up. It includes a memory controller and also bridges the gap between the cpu and memory. That is also where the AGP slot directly connects to. Because the video card wants to get a hold of the RAM's data ASAP.

Very well explained people!!

I managed to grasp that without much difficulty, and DrMDJ I can see what you are saying.

Thanks for all the help, its appreciated!

Hong

I thought someone might bring up the Northbridge/Southbridge stuff. The problem with bringing these in to the discussion is that whereas at one time motherboards were all using the North/South Bridge chipset architecture, for a while now that hasn't been the case (though it still does exist in boards). Intel abandoned it and went to its "hub" (Intel Hub Architecture) configuration which appeared beginning with its i8xx based boards. Nvidia has at the very least "evolved" the architecture quite a bit with its "port" design in to what a lot of people consider not to be a north/south bridge architecture.

Geez, i havent even learn about the north/southbridge stuff yet and already its becoming obsolete.

Technology is soooo hard to keep up with!!

Anyways, with the help from here I should (hopefully) manage :)

Thanks all

Hong